Static Timing Analysis for Nanometer Designs - A Practical Approach

Contents

Preface

Introduction

1.1 Nanometer Designs

1.2 What is Static Timing Analysis?

1.3 Why Static Timing Analysis?

1.4 Design Flow

1.4.1 CMOS Digital Designs

1.4.2 FPGA Designs

1.4.3 Asynchronous Designs

1.5 STA at Different Design Phases

1.6 Limitations of Static Timing Analysis

1.7 Power Considerations

1.8 Reliability Considerations

1.9 Outline of the Book

STA Concepts

2.1 CMOS Logic Design

2.1.1 Basic MOS Structure

2.1.2 CMOS Logic Gate

2.1.3 Standard Cells

2.2 Modeling of CMOS Cells

2.3 Switching Waveform

2.4 Propagation Delay

2.5 Slew of a Waveform

2.6 Skew between Signals

2.7 Timing Arcs and Unateness

2.8 Min and Max Timing Paths

2.9 Clock Domains

2.10 Operating Conditions

Standard Cell Library

3.1 Pin Capacitance

3.2 Timing Modeling

3.2.1 Linear Timing Model

3.2.2 Non-Linear Delay Model

3.2.3 Threshold Specifications and Slew Derating

3.3 Timing Models - Combinational Cells

3.3.1 Delay and Slew Models

3.3.2 General Combinational Block

3.4 Timing Models - Sequential Cells

3.4.1 Synchronous Checks: Setup and Hold

3.4.2 Asynchronous Checks

3.4.3 Propagation Delay

3.5 State- Dependent Models

3.6 Interface Timing Model for a Black Box

3.7 Advanced Timing Modeling

3.7.1 Receiver Pin Capacitance

3.7.2 Output Current

3.7.3 Models for Crosstalk Noise Analysis

3.7.4 Other Noise Models

3.8 Power Dissipation Modeling

3.8.1 Active Power

3.8.2 Leakage Power

3.9 Other Attributes in Cell Library

3.10 Characterization and Operating Conditions

3.10.1 Derating using K-factors

3.10.2 Library Units

Interconnect Parasitics

4.1 RLC for Interconnect

4.2 Wireload Models

4.2.1 Interconnect Trees

4.2.2 Specifying Wireload Models

4.3 Representation of Extracted Parasitics

4.3.1 Detailed Standard Parasitic Format

4.3.2 Reduced Standard Parasitic Format

4.3.3 Standard Parasitic Exchange Format

4.4 Representing Coupling Capacitances

4.5 Hierarchical Methodology

4.6 Reducing Parasitics for Critical Nets

Delay Calculation

5.1 Overview

5.1.1 Delay Calculation Basics

5.1.2 Delay Calculation with Interconnect

5.2 Cell Delay using Effective Capacitance

5.3 Interconnect Delay

5.4 Slew Merging

5.5 Different Slew Thresholds

5.6 Different Voltage Domains

5.7 Path Delay Calculation

5.7.1 Combinational Path Delay

5.7.2 Path to a Flip- flop

5.7.3 Multiple Paths

5.8 Slack Calculation

Crosstalk and Noise

6.1 Overview

6.2 Crosstalk Glitch Analysis

6.2.1 Basics

6.2.2 Types of Glitches

6.2.3 Glitch Thresholds and Propagation

6.2.4 Noise Accumulation with Multiple Aggressors

6.2.5 Aggressor Timing Correlation

6.2.6 Aggressor Functional Correlation

6.3 Crosstalk Delay Analysis

6.3.1 Basics

6.3.2 Positive and Negative Crosstalk

6.3.3 Accumulation with Multiple Aggressors

6.3.4 Aggressor Victim Timing Correlation

6.3.5 Aggressor Victim Functional Correlation

6.4 Timing Verification Using Crosstalk Delay

6.4.1 Setup Analysis

6.4.2 Hold Analysis

6.5 Computational Complexity

6.6 Noise Avoidance Techniques

Configuring the STA Environment

7.1 What is the STA Environment?

7.2 Specifying Clocks

7.2.1 Clock Uncertainty

7.2.2 Clock Latency

7.3 Generated Clocks

7.4 Constraining Input Paths

7.5 Constraining Output Paths

7.6 Timing Path Groups

7.7 Modeling of External Attributes

7.7.1 Modeling Drive Strengths

7.7.2 Modeling Capacitive Load

7.8 Design Rule Checks

7.9 Virtual Clocks

7.10 Refining the Timing Analysis

7.10.1 Specifying Inactive Signals

7.10.2 Breaking Timing Arcs in Cells

7.11 Point-to-Point Specification

7.12 Path Segmentation

Timing Verification

8.1 Setup Timing Check

8.1.1 Flip-flop to Flip-flop Path

8.1.2 Input to Flip- flop Path

8.1.3 Flip- flop to Output Path

8.1.4 Input to Output Path

8.1.5 Frequency Histogram

8.2 Hold Timing Check

8.2.1 Flip- flop to Flip-flop Path

8.2.2 Input to Flip-flop Path

8.2.3 Flip- flop to Output Path

8.2.4 Input to Output Path

8.3 Multicycle Paths

8.4 False Paths

8.5 Half-Cycle Paths

8.6 Removal Timing Check

8.7 Recovery Timing Check

8.8 Timing across Clock Domains

8.8.1 Slow to Fast Clock Domains

8.8.2 Fast to Slow Clock Domains

8.9 Examples

8.10 Multiple Clocks

8.10.1 Integer Multiples

8.10.2 Non-Integer Multiples

8.10.3 Phase Shifted

Interface Analysis

9.1 IO Interfaces

9.1.1 Input Interface

9.1.2 Output Interface

9.1.3 Output Change within Window

9.2 SRAM Interface

9.3 DDR SDRAM Interface

9.3.1 Read Cycle

9.3.2 Write Cycle

9.4 Interface to a Video DAC

Robust Verification

10.1 On-Chip Variations

10.2 Time Borrowing

10.3 Data to Data Checks

10.4 Non-Sequential Checks

10.5 Clock Gating Checks

10.6 Power Management

10.6.1 Clock Gating

10.6.2 Power Gating

10.6.3 Multi Vt Cells

10.6.4 Well Bias

10.7 Backannotation

10.7.1 SPEF

10.7.2 SDF

10.8 Sign-off Methodology

10.9 Statistical Static Timing Analysis

10.9.1 Process and Interconnect Variations

10.9.2 Statistical Analysis

10.10 Paths Failing Timing?

10.11 Validating Timing Constraints

SDC

A. 1 Basic Commands

A.2 Object Access Commands

A.3 Timing Constraints

A.4 Environment Commands

A. 5 Multi-Voltage Commands

Standard Delay Format ( SDF)

B. 1 What is it?

B.2 The Format

B.2.1 Examples

B.3 The Annotation Process

B. 3.1 Verilog HDL

B.3.2 VHDL

B.4 Mapping Examples

B.5 Complete Syntax

Standard Parasitic Extraction Format ( SPEF)

C.1 Basics

C. 2 Format

C. 3 Complete Syntax

Bibliography

Index